Panoramica della PMU

L'unità di monitoraggio delle prestazioni (PMU) è un componente hardware all'interno del core della CPU che monitora il modo in cui il processore esegue il codice. Quando attivi la PMU in un'istanza Compute Engine A4X, C4A, C4 o M4, puoi accedere ai contatori delle prestazioni nella PMU utilizzando un software di monitoraggio delle prestazioni. Questo approccio ti consente di ottimizzare i workload sensibili alle prestazioni, come il computing ad alte prestazioni (HPC) o il machine learning (ML), aiutandoti a identificare e risolvere i colli di bottiglia delle prestazioni nelle tue applicazioni.

Questo documento spiega il comportamento, la fatturazione e le limitazioni dell'unità di gestione dell'alimentazione. Per scoprire come attivare la PMU in un'istanza A4X, C4A, C4 o M4, consulta Attivare la PMU nelle istanze Compute Engine.

Comprendere la PMU

La PMU è composta da un insieme di contatori hardware chiamati contatori di monitoraggio delle prestazioni (PMC). Questi contatori sono registri specifici del modello che conteggiano ogni volta che si verifica un evento del processore di basso livello all'interno della CPU, ad esempio un errore di previsione del ramo o un fallimento della cache. Puoi leggere e configurare i PMC nella PMU utilizzando software di monitoraggio delle prestazioni come Intel VTune Profiler.

Dopo aver attivato la PMU in un'istanza di calcolo, la PMU viene eseguita in background, monitorando continuamente gli eventi di prestazioni utilizzando i PMC. Se vuoi, puoi configurare le soglie per PMC specifiche utilizzando il software di monitoraggio delle prestazioni che preferisci. Se un contatore delle prestazioni supera la soglia designata, la PMU invia una notifica al software.

Eventi PMU

Per impostazione predefinita, la PMU è disabilitata nelle istanze di computing. Per abilitarla, specifica i tipi di eventi CPU di basso livello da monitorare attivando uno dei seguenti tipi di PMU:

  • Architettura (ARCHITECTURAL): puoi misurare i seguenti eventi di rendimento dell'architettura:
    • Istruzioni di ramificazione ritirate: il numero di istruzioni di ramificazione ritirate. Utilizza questo evento per misurare l'esecuzione del codice e identificare potenziali colli di bottiglia delle prestazioni.
    • Branch misses retired: il numero di istruzioni di diramazione che sono state previste in modo errato, causando l'arresto del processore e l'eliminazione delle istruzioni recuperate. Se vedi un numero elevato per questo evento, puoi probabilmente ottimizzare le prestazioni della CPU.
    • Istruzioni ritirate: il numero di istruzioni che la CPU elabora correttamente. Utilizza questo evento per misurare la velocità effettiva delle istruzioni della CPU.
    • Slot top-down: il numero di slot disponibili all'interno della pipeline di un processore che vengono utilizzati per eseguire simultaneamente le istruzioni. Utilizza questo evento per capire con quanta efficienza il tuo codice utilizza le risorse del processore.
    • Cicli core non interrotti: il numero di cicli core quando il thread non è interrotto, ad esempio a causa della gestione dell'alimentazione o di interruzioni. Utilizza questo evento per valutare l'utilizzo complessivo del processore.
    • Cicli di riferimento non interrotti: il numero di cicli di riferimento quando il core non è interrotto, ad esempio durante il recupero di dati o istruzioni. Il core viene arrestato quando esegue le istruzioni HLT o MWAIT. I cicli di riferimento funzionano a una frequenza fissa, fornendo un riferimento temporale stabile anche quando la velocità del processore cambia per preservare l'energia. Utilizza questo evento per misurare il tempo dedicato a un'attività e identificare i colli di bottiglia delle prestazioni nel codice.
  • Standard (STANDARD): puoi misurare tutti gli eventi del tipo di PMU Architettura e tutti gli eventi locali all'interno del core della CPU, inclusi gli eventi della cache di livello 2 (L2).
  • Avanzata (ENHANCED): puoi misurare tutti gli eventi dal tipo di PMU Standard e qualsiasi evento locale al di fuori del core della CPU, inclusi gli eventi della cache di livello 3 (L3).

Serie di macchine e piattaforme CPU supportate

Puoi attivare la PMU sulle istanze di computing che utilizzano le seguenti serie di macchine e piattaforme CPU:

Piattaforma CPU Serie di macchine Tipi di monitoraggio PMU
Processore Google Axion C4A ARCHITECTURAL e STANDARD
Processore scalabile Intel Xeon (Emerald Rapids) di 5ª generazione C4 e M4 ARCHITECTURAL, STANDARD e ENHANCED
Processore Intel Xeon Scalable (Granite Rapids) di 6ª generazione C4 ARCHITECTURAL, STANDARD e ENHANCED
Processore NVIDIA Grace A4X ARCHITECTURAL e STANDARD

Eventi PMU supportati per piattaforma CPU

Le tabelle seguenti elencano gli eventi PMU supportati per piattaforma CPU:

Google Axion

La tabella seguente elenca gli eventi PMU supportati per i processori Google Axion con core Armv9 Neoverse V2.

Codice evento Tipo di monitoraggio PMU Nome evento
0x0 ARCHITETTONICO SW_INCR
0x3 ARCHITETTONICO L1D_CACHE_REFILL
0x4 ARCHITETTONICO L1D_CACHE
0x8 ARCHITETTONICO INST_RETIRED
0x10 ARCHITETTONICO BR_MIS_PRED
0x11 ARCHITETTONICO CPU_CYCLES
0x12 ARCHITETTONICO BR_PRED
0x1b ARCHITETTONICO INST_SPEC
0x1e ARCHITETTONICO CHAIN
0x23 ARCHITETTONICO STALL_FRONTEND
0x24 ARCHITETTONICO STALL_BACKEND
0x39 ARCHITETTONICO L1D_CACHE_LMISS_RD
0x3c ARCHITETTONICO STALL
0x40 ARCHITETTONICO L1D_CACHE_RD
0x4006 ARCHITETTONICO L1I_CACHE_LMISS
0x8006 ARCHITETTONICO SVE_INST_SPEC
0x0 STANDARD SW_INCR
0x1 STANDARD L1I_CACHE_REFILL
0x2 STANDARD L1I_TLB_REFILL
0x3 STANDARD L1D_CACHE_REFILL
0x4 STANDARD L1D_CACHE
0x5 STANDARD L1D_TLB_REFILL
0x8 STANDARD INST_RETIRED
0x9 STANDARD EXC_TAKEN
0xa STANDARD EXC_RETURN
0xb STANDARD CID_WRITE_RETIRED
0x10 STANDARD BR_MIS_PRED
0x11 STANDARD CPU_CYCLES
0x12 STANDARD BR_PRED
0x13 STANDARD MEM_ACCESS
0x14 STANDARD L1I_CACHE
0x15 STANDARD L1D_CACHE_WB
0x16 STANDARD L2D_CACHE
0x17 STANDARD L2D_CACHE_REFILL
0x18 STANDARD L2D_CACHE_WB
0x19 STANDARD BUS_ACCESS
0x1b STANDARD INST_SPEC
0x1c STANDARD TTBR_WRITE_RETIRED
0x1d STANDARD BUS_CYCLES
0x1e STANDARD CHAIN
0x20 STANDARD L2D_CACHE_ALLOCATE
0x21 STANDARD BR_RETIRED
0x22 STANDARD BR_MIS_PRED_RETIRED
0x23 STANDARD STALL_FRONTEND
0x24 STANDARD STALL_BACKEND
0x25 STANDARD L1D_TLB
0x26 STANDARD L1I_TLB
0x2d STANDARD L2D_TLB_REFILL
0x2f STANDARD L2D_TLB
0x31 STANDARD REMOTE_ACCESS
0x34 STANDARD DTLB_WALK
0x35 STANDARD ITLB_WALK
0x39 STANDARD L1D_CACHE_LMISS_RD
0x3a STANDARD OP_RETIRED
0x3b STANDARD OP_SPEC
0x3c STANDARD STALL
0x3d STANDARD STALL_SLOT_BACKEND
0x3e STANDARD STALL_SLOT_FRONTEND
0x3f STANDARD STALL_SLOT
0x40 STANDARD L1D_CACHE_RD
0x41 STANDARD L1D_CACHE_WR
0x42 STANDARD L1D_CACHE_REFILL_RD
0x43 STANDARD L1D_CACHE_REFILL_WR
0x44 STANDARD L1D_CACHE_REFILL_INNER
0x45 STANDARD L1D_CACHE_REFILL_OUTER
0x46 STANDARD L1D_CACHE_WB_VICTIM
0x47 STANDARD L1D_CACHE_WB_CLEAN
0x48 STANDARD L1D_CACHE_INVAL
0x4c STANDARD L1D_TLB_REFILL_RD
0x4d STANDARD L1D_TLB_REFILL_WR
0x4e STANDARD L1D_TLB_RD
0x4f STANDARD L1D_TLB_WR
0x50 STANDARD L2D_CACHE_RD
0x51 STANDARD L2D_CACHE_WR
0x52 STANDARD L2D_CACHE_REFILL_RD
0x53 STANDARD L2D_CACHE_REFILL_WR
0x56 STANDARD L2D_CACHE_WB_VICTIM
0x57 STANDARD L2D_CACHE_WB_CLEAN
0x58 STANDARD L2D_CACHE_INVAL
0x5c STANDARD L2D_TLB_REFILL_RD
0x5d STANDARD L2D_TLB_REFILL_WR
0x5e STANDARD L2D_TLB_RD
0x5f STANDARD L2D_TLB_WR
0x60 STANDARD BUS_ACCESS_RD
0x61 STANDARD BUS_ACCESS_WR
0x66 STANDARD MEM_ACCESS_RD
0x67 STANDARD MEM_ACCESS_WR
0x68 STANDARD UNALIGNED_LD_SPEC
0x69 STANDARD UNALIGNED_ST_SPEC
0x6a STANDARD UNALIGNED_LDST_SPEC
0x6c STANDARD LDREX_SPEC
0x6d STANDARD STREX_PASS_SPEC
0x6e STANDARD STREX_FAIL_SPEC
0x6f STANDARD STREX_SPEC
0x70 STANDARD LD_SPEC
0x71 STANDARD ST_SPEC
0x73 STANDARD DP_SPEC
0x74 STANDARD ASE_SPEC
0x75 STANDARD VFP_SPEC
0x76 STANDARD PC_WRITE_SPEC
0x77 STANDARD CRYPTO_SPEC
0x78 STANDARD BR_IMMED_SPEC
0x79 STANDARD BR_RETURN_SPEC
0x7a STANDARD BR_INDIRECT_SPEC
0x7c STANDARD ISB_SPEC
0x7d STANDARD DSB_SPEC
0x7e STANDARD DMB_SPEC
0x81 STANDARD EXC_UNDEF
0x82 STANDARD EXC_SVC
0x83 STANDARD EXC_PABORT
0x84 STANDARD EXC_DABORT
0x86 STANDARD EXC_IRQ
0x87 STANDARD EXC_FIQ
0x88 STANDARD EXC_SMC
0x8a STANDARD EXC_HVC
0x8b STANDARD EXC_TRAP_PABORT
0x8c STANDARD EXC_TRAP_DABORT
0x8d STANDARD EXC_TRAP_OTHER
0x8e STANDARD EXC_TRAP_IRQ
0x8f STANDARD EXC_TRAP_FIQ
0x90 STANDARD RC_LD_SPEC
0x91 STANDARD RC_ST_SPEC
0x4004 STANDARD CNT_CYCLES
0x4005 STANDARD STALL_BACKEND_MEM
0x4006 STANDARD L1I_CACHE_LMISS
0x4009 STANDARD L2D_CACHE_LMISS_RD
0x4020 STANDARD LDST_ALIGN_LAT
0x4021 STANDARD LD_ALIGN_LAT
0x4022 STANDARD ST_ALIGN_LAT
0x8005 STANDARD ASE_INST_SPEC
0x8006 STANDARD SVE_INST_SPEC
0x8014 STANDARD FP_HP_SPEC
0x8018 STANDARD FP_SP_SPEC
0x801c STANDARD FP_DP_SPEC
0x8074 STANDARD SVE_PRED_SPEC
0x8075 STANDARD SVE_PRED_EMPTY_SPEC
0x8076 STANDARD SVE_PRED_FULL_SPEC
0x8077 STANDARD SVE_PRED_PARTIAL_SPEC
0x8079 STANDARD SVE_PRED_NOT_FULL_SPEC
0x80bc STANDARD SVE_LDFF_SPEC
0x80bd STANDARD SVE_LDFF_FAULT_SPEC
0x80c0 STANDARD FP_SCALE_OPS_SPEC
0x80c1 STANDARD FP_FIXED_OPS_SPEC
0x80e3 STANDARD ASE_SVE_INT8_SPEC
0x80e7 STANDARD ASE_SVE_INT16_SPEC
0x80eb STANDARD ASE_SVE_INT32_SPEC
0x80ef STANDARD ASE_SVE_INT64_SPEC

Intel Emerald Rapids

La tabella seguente elenca gli eventi PMU supportati per i processori Intel Emerald Rapids (EMR) di 5ª generazione.

Codice evento UMask Tipo di monitoraggio PMU Nome evento
0x03 0x04 STANDARD LD_BLOCKS.ADDRESS_ALIAS
0x03 0x82 STANDARD LD_BLOCKS.STORE_FORWARD
0x03 0x88 STANDARD LD_BLOCKS.NO_SR
0x11 0x02 STANDARD ITLB_MISSES.WALK_COMPLETED_4K
0x11 0x04 STANDARD ITLB_MISSES.WALK_COMPLETED_2M_4M
0x11 0x0E STANDARD ITLB_MISSES.WALK_COMPLETED
0x11 0x10 STANDARD ITLB_MISSES.WALK_ACTIVE
0x11 0x20 STANDARD ITLB_MISSES.STLB_HIT
0x12 0x02 STANDARD DTLB_LOAD_MISSES.WALK_COMPLETED_4K
0x12 0x04 STANDARD DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M
0x12 0x08 STANDARD DTLB_LOAD_MISSES.WALK_COMPLETED_1G
0x12 0x0E STANDARD DTLB_LOAD_MISSES.WALK_COMPLETED
0x12 0x10 STANDARD DTLB_LOAD_MISSES.WALK_ACTIVE
0x12 0x20 STANDARD DTLB_LOAD_MISSES.STLB_HIT
0x13 0x02 STANDARD DTLB_STORE_MISSES.WALK_COMPLETED_4K
0x13 0x04 STANDARD DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
0x13 0x08 STANDARD DTLB_STORE_MISSES.WALK_COMPLETED_1G
0x13 0x0E STANDARD DTLB_STORE_MISSES.WALK_COMPLETED
0x13 0x10 STANDARD DTLB_STORE_MISSES.WALK_ACTIVE
0x13 0x20 STANDARD DTLB_STORE_MISSES.STLB_HIT
0x20 0x04 AVANZATO OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO
0x20 0x08 AVANZATO OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
0x21 0x01 AVANZATO OFFCORE_REQUESTS.DEMAND_DATA_RD
0x21 0x08 AVANZATO OFFCORE_REQUESTS.DATA_RD
0x21 0x80 AVANZATO OFFCORE_REQUESTS.ALL_REQUESTS
0x24 0x21 STANDARD L2_RQSTS.DEMAND_DATA_RD_MISS
0x24 0x22 STANDARD L2_RQSTS.RFO_MISS
0x24 0x24 STANDARD L2_RQSTS.CODE_RD_MISS
0x24 0x27 STANDARD L2_RQSTS.ALL_DEMAND_MISS
0x24 0x28 STANDARD L2_RQSTS.SWPF_MISS
0x24 0x3F STANDARD L2_RQSTS.MISS
0x24 0xC1 STANDARD L2_RQSTS.DEMAND_DATA_RD_HIT
0x24 0xC2 STANDARD L2_RQSTS.RFO_HIT
0x24 0xC4 STANDARD L2_RQSTS.CODE_RD_HIT
0x24 0xC8 STANDARD L2_RQSTS.SWPF_HIT
0x24 0xE1 STANDARD L2_RQSTS.ALL_DEMAND_DATA_RD
0x24 0xE2 STANDARD L2_RQSTS.ALL_RFO
0x24 0xE4 STANDARD L2_RQSTS.ALL_CODE_RD
0x24 0xE7 STANDARD L2_RQSTS.ALL_DEMAND_REFERENCES
0x24 0xFF STANDARD L2_RQSTS.REFERENCES
0x25 0x1F STANDARD L2_LINES_IN.ALL
0x26 0x01 STANDARD L2_LINES_OUT.SILENT
0x26 0x02 STANDARD L2_LINES_OUT.NON_SILENT
0x2D 0x01 AVANZATO XQ.FULL_CYCLES
0x2E 0x41 AVANZATO LONGEST_LAT_CACHE.MISS
0x3C 0x00 ARCHITETTONICO CPU_CLK_UNHALTED.THREAD_P
0x40 0x01 STANDARD SW_PREFETCH_ACCESS.NTA
0x40 0x02 STANDARD SW_PREFETCH_ACCESS.T0
0x40 0x04 STANDARD SW_PREFETCH_ACCESS.T1_T2
0x40 0x08 STANDARD SW_PREFETCH_ACCESS.PREFETCHW
0x43 0xFD STANDARD MEM_LOAD_COMPLETED.L1_MISS_ANY
0x44 0x01 STANDARD MEM_STORE_RETIRED.L2_HIT
0x47 0x02 STANDARD MEMORY_ACTIVITY.CYCLES_L1D_MISS
0x47 0x03 STANDARD MEMORY_ACTIVITY.STALLS_L1D_MISS
0x47 0x05 STANDARD MEMORY_ACTIVITY.STALLS_L2_MISS
0x47 0x09 AVANZATO MEMORY_ACTIVITY.STALLS_L3_MISS
0x48 0x01 STANDARD L1D_PEND_MISS.PENDING
0x48 0x02 STANDARD L1D_PEND_MISS.FB_FULL
0x48 0x04 STANDARD L1D_PEND_MISS.L2_STALL
0x4C 0x01 STANDARD LOAD_HIT_PREFETCH.SWPF
0x51 0x01 STANDARD L1D.REPLACEMENT
0x54 0x01 AVANZATO TX_MEM.ABORT_CONFLICT
0x54 0x02 AVANZATO TX_MEM.ABORT_CAPACITY_WRITE
0x54 0x80 AVANZATO TX_MEM.ABORT_CAPACITY_READ
0x61 0x02 STANDARD DSB2MITE_SWITCHES.PENALTY_CYCLES
0x75 0x01 STANDARD INST_DECODED.DECODERS
0x76 0x01 STANDARD UOPS_DECODED.DEC0_UOPS
0x79 0x04 STANDARD IDQ.MITE_CYCLES_ANY
0x79 0x08 STANDARD IDQ.DSB_CYCLES_ANY
0x79 0x20 STANDARD IDQ.MS_CYCLES_ANY
0x80 0x04 STANDARD ICACHE_DATA.STALLS
0x83 0x04 STANDARD ICACHE_TAG.STALLS
0x87 0x01 STANDARD DECODE.LCP
0x9C 0x01 STANDARD IDQ_UOPS_NOT_DELIVERED.CORE
0xA2 0x02 STANDARD RESOURCE_STALLS.SCOREBOARD
0xA2 0x08 STANDARD RESOURCE_STALLS.SB
0xA3 0x01 STANDARD CYCLE_ACTIVITY.CYCLES_L2_MISS
0xA3 0x04 STANDARD CYCLE_ACTIVITY.STALLS_TOTAL
0xA3 0x05 STANDARD CYCLE_ACTIVITY.STALLS_L2_MISS
0xA3 0x06 AVANZATO CYCLE_ACTIVITY.STALLS_L3_MISS
0xA3 0x08 STANDARD CYCLE_ACTIVITY.CYCLES_L1D_MISS
0xA3 0x0C STANDARD CYCLE_ACTIVITY.STALLS_L1D_MISS
0xA3 0x10 STANDARD CYCLE_ACTIVITY.CYCLES_MEM_ANY
0xA4 0x01 ARCHITETTONICO TOPDOWN.SLOTS_P
0xA4 0x02 STANDARD TOPDOWN.BACKEND_BOUND_SLOTS
0xA4 0x04 STANDARD TOPDOWN.BAD_SPEC_SLOTS
0xA4 0x08 STANDARD TOPDOWN.BR_MISPREDICT_SLOTS
0xA4 0x10 STANDARD TOPDOWN.MEMORY_BOUND_SLOTS
0xA5 0x07 STANDARD RS_EMPTY.CYCLES
0xA6 0x02 STANDARD EXE_ACTIVITY.1_PORTS_UTIL
0xA6 0x04 STANDARD EXE_ACTIVITY.2_PORTS_UTIL
0xA6 0x08 STANDARD EXE_ACTIVITY.3_PORTS_UTIL
0xA6 0x10 STANDARD EXE_ACTIVITY.4_PORTS_UTIL
0xA6 0x21 STANDARD EXE_ACTIVITY.BOUND_ON_LOADS
0xA6 0x40 STANDARD EXE_ACTIVITY.BOUND_ON_STORES
0xA6 0x80 STANDARD EXE_ACTIVITY.EXE_BOUND_0_PORTS
0xA8 0x01 STANDARD LSD.CYCLES_ACTIVE
0xAD 0x01 STANDARD INT_MISC.RECOVERY_CYCLES
0xAD 0x10 STANDARD INT_MISC.UOP_DROPPING
0xAD 0x20 STANDARD INT_MISC.MBA_STALLS
0xAD 0x80 STANDARD INT_MISC.CLEAR_RESTEER_CYCLES
0xAE 0x01 STANDARD UOPS_ISSUED.ANY
0xB0 0x01 STANDARD ARITH.FP_DIVIDER_ACTIVE
0xB0 0x08 STANDARD ARITH.IDIV_ACTIVE
0xB0 0x09 STANDARD ARITH.DIVIDER_ACTIVE
0xB1 0x01 STANDARD UOPS_EXECUTED.CYCLES_GE_1
0xB1 0x02 STANDARD UOPS_EXECUTED.CORE
0xB1 0x10 STANDARD UOPS_EXECUTED.X87
0xB2 0x01 STANDARD UOPS_DISPATCHED.PORT_0
0xB2 0x02 STANDARD UOPS_DISPATCHED.PORT_1
0xB2 0x04 STANDARD UOPS_DISPATCHED.PORT_2_3_10
0xB2 0x10 STANDARD UOPS_DISPATCHED.PORT_4_9
0xB2 0x20 STANDARD UOPS_DISPATCHED.PORT_5_11
0xB2 0x40 STANDARD UOPS_DISPATCHED.PORT_6
0xB2 0x80 STANDARD UOPS_DISPATCHED.PORT_7_8
0xB3 0x01 STANDARD FP_ARITH_DISPATCHED.PORT_0
0xB3 0x02 STANDARD FP_ARITH_DISPATCHED.PORT_1
0xB3 0x04 STANDARD FP_ARITH_DISPATCHED.PORT_5
0xB7 0x02 STANDARD EXE.AMX_BUSY
0xC0 0x00 ARCHITETTONICO INST_RETIRED.ANY_P
0xC0 0x02 STANDARD INST_RETIRED.NOP
0xC0 0x08 STANDARD INST_RETIRED.REP_ITERATION
0xC0 0x10 STANDARD INST_RETIRED.MACRO_FUSED
0xC1 0x02 STANDARD ASSISTS.FP
0xC1 0x08 STANDARD ASSISTS.PAGE_FAULT
0xC1 0x10 STANDARD ASSISTS.SSE_AVX_MIX
0xC1 0x1B STANDARD ASSISTS.ANY
0xC2 0x01 STANDARD UOPS_RETIRED.HEAVY
0xC2 0x02 STANDARD UOPS_RETIRED.SLOTS
0xC3 0x01 STANDARD MACHINE_CLEARS.COUNT
0xC3 0x02 STANDARD MACHINE_CLEARS.MEMORY_ORDERING
0xC3 0x04 STANDARD MACHINE_CLEARS.SMC
0xC4 0x00 ARCHITETTONICO BR_INST_RETIRED.ALL_BRANCHES
0xC4 0x01 STANDARD BR_INST_RETIRED.COND_TAKEN
0xC4 0x02 STANDARD BR_INST_RETIRED.NEAR_CALL
0xC4 0x08 STANDARD BR_INST_RETIRED.NEAR_RETURN
0xC4 0x10 STANDARD BR_INST_RETIRED.COND_NTAKEN
0xC4 0x11 STANDARD BR_INST_RETIRED.COND
0xC4 0x20 STANDARD BR_INST_RETIRED.NEAR_TAKEN
0xC4 0x40 STANDARD BR_INST_RETIRED.FAR_BRANCH
0xC4 0x80 STANDARD BR_INST_RETIRED.INDIRECT
0xC5 0x00 ARCHITETTONICO BR_MISP_RETIRED.ALL_BRANCHES
0xC5 0x01 STANDARD BR_MISP_RETIRED.COND_TAKEN
0xC5 0x02 STANDARD BR_MISP_RETIRED.INDIRECT_CALL
0xC5 0x08 STANDARD BR_MISP_RETIRED.RET
0xC5 0x10 STANDARD BR_MISP_RETIRED.COND_NTAKEN
0xC5 0x11 STANDARD BR_MISP_RETIRED.COND
0xC5 0x20 STANDARD BR_MISP_RETIRED.NEAR_TAKEN
0xC5 0x80 STANDARD BR_MISP_RETIRED.INDIRECT
0xC7 0x01 STANDARD FP_ARITH_INST_RETIRED.SCALAR_DOUBLE
0xC7 0x02 STANDARD FP_ARITH_INST_RETIRED.SCALAR_SINGLE
0xC7 0x04 STANDARD FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE
0xC7 0x08 STANDARD FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE
0xC7 0x10 STANDARD FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE
0xC7 0x20 STANDARD FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE
0xC7 0x40 STANDARD FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE
0xC7 0x80 STANDARD FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE
0xC9 0x01 AVANZATO RTM_RETIRED.START
0xC9 0x02 AVANZATO RTM_RETIRED.COMMIT
0xC9 0x04 AVANZATO RTM_RETIRED.ABORTED
0xC9 0x08 AVANZATO RTM_RETIRED.ABORTED_MEM
0xC9 0x20 AVANZATO RTM_RETIRED.ABORTED_UNFRIENDLY
0xC9 0x40 AVANZATO RTM_RETIRED.ABORTED_MEMTYPE
0xC9 0x80 AVANZATO RTM_RETIRED.ABORTED_EVENTS
0xCE 0x01 STANDARD AMX_OPS_RETIRED.INT8
0xCE 0x02 STANDARD AMX_OPS_RETIRED.BF16
0xCF 0x01 STANDARD FP_ARITH_INST_RETIRED2.SCALAR_HALF
0xCF 0x02 STANDARD FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF
0xCF 0x03 STANDARD FP_ARITH_INST_RETIRED2.SCALAR
0xCF 0x04 STANDARD FP_ARITH_INST_RETIRED2.128B_PACKED_HALF
0xCF 0x08 STANDARD FP_ARITH_INST_RETIRED2.256B_PACKED_HALF
0xCF 0x10 STANDARD FP_ARITH_INST_RETIRED2.512B_PACKED_HALF
0xCF 0x1C STANDARD FP_ARITH_INST_RETIRED2.VECTOR
0xD0 0x11 STANDARD MEM_INST_RETIRED.STLB_MISS_LOADS
0xD0 0x12 STANDARD MEM_INST_RETIRED.STLB_MISS_STORES
0xD0 0x21 STANDARD MEM_INST_RETIRED.LOCK_LOADS
0xD0 0x41 STANDARD MEM_INST_RETIRED.SPLIT_LOADS
0xD0 0x42 STANDARD MEM_INST_RETIRED.SPLIT_STORES
0xD0 0x81 STANDARD MEM_INST_RETIRED.ALL_LOADS
0xD0 0x82 STANDARD MEM_INST_RETIRED.ALL_STORES
0xD0 0x83 STANDARD MEM_INST_RETIRED.ANY
0xD1 0x01 STANDARD MEM_LOAD_RETIRED.L1_HIT
0xD1 0x02 STANDARD MEM_LOAD_RETIRED.L2_HIT
0xD1 0x04 AVANZATO MEM_LOAD_RETIRED.L3_HIT
0xD1 0x08 STANDARD MEM_LOAD_RETIRED.L1_MISS
0xD1 0x10 STANDARD MEM_LOAD_RETIRED.L2_MISS
0xD1 0x20 AVANZATO MEM_LOAD_RETIRED.L3_MISS
0xD1 0x40 STANDARD MEM_LOAD_RETIRED.FB_HIT
0xD2 0x01 AVANZATO MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS
0xD2 0x02 AVANZATO MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD
0xD2 0x04 AVANZATO MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD
0xD2 0x08 AVANZATO MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE
0xD3 0x01 AVANZATO MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM
0xD3 0x02 AVANZATO MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM
0xD3 0x04 AVANZATO MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM
0xD3 0x08 AVANZATO MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD
0xD4 0x04 STANDARD MEM_LOAD_MISC_RETIRED.UC
0xE0 0x20 STANDARD MISC2_RETIRED.LFENCE
0xE5 0x03 STANDARD MEM_UOP_RETIRED.ANY
0xE7 0x03 STANDARD INT_VEC_RETIRED.ADD_128
0xE7 0x0C STANDARD INT_VEC_RETIRED.ADD_256
0xE7 0x10 STANDARD INT_VEC_RETIRED.VNNI_128
0xE7 0x13 STANDARD INT_VEC_RETIRED.128BIT
0xE7 0x20 STANDARD INT_VEC_RETIRED.VNNI_256
0xE7 0x40 STANDARD INT_VEC_RETIRED.SHUFFLES
0xE7 0x80 STANDARD INT_VEC_RETIRED.MUL_256
0xE7 0xAC STANDARD INT_VEC_RETIRED.256BIT
0xEC 0x10 STANDARD CPU_CLK_UNHALTED.C01
0xEC 0x20 STANDARD CPU_CLK_UNHALTED.C02
0xEC 0x40 STANDARD CPU_CLK_UNHALTED.PAUSE
0xEC 0x70 STANDARD CPU_CLK_UNHALTED.C0_WAIT

Intel Granite Rapids

La tabella seguente elenca gli eventi PMU supportati per i processori Intel Granite Rapids di 6ª generazione.

Codice evento UMask Tipo di monitoraggio PMU Nome evento
0x03 0x04 STANDARD LD_BLOCKS.ADDRESS_ALIAS
0x03 0x82 STANDARD LD_BLOCKS.STORE_FORWARD
0x03 0x88 STANDARD LD_BLOCKS.NO_SR
0x11 0x02 STANDARD ITLB_MISSES.WALK_COMPLETED_4K
0x11 0x04 STANDARD ITLB_MISSES.WALK_COMPLETED_2M_4M
0x11 0x0E STANDARD ITLB_MISSES.WALK_COMPLETED
0x11 0x10 STANDARD ITLB_MISSES.WALK_ACTIVE
0x11 0x20 STANDARD ITLB_MISSES.STLB_HIT
0x12 0x02 STANDARD DTLB_LOAD_MISSES.WALK_COMPLETED_4K
0x12 0x04 STANDARD DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M
0x12 0x08 STANDARD DTLB_LOAD_MISSES.WALK_COMPLETED_1G
0x12 0x0E STANDARD DTLB_LOAD_MISSES.WALK_COMPLETED
0x12 0x10 STANDARD DTLB_LOAD_MISSES.WALK_ACTIVE
0x12 0x20 STANDARD DTLB_LOAD_MISSES.STLB_HIT
0x13 0x02 STANDARD DTLB_STORE_MISSES.WALK_COMPLETED_4K
0x13 0x04 STANDARD DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
0x13 0x08 STANDARD DTLB_STORE_MISSES.WALK_COMPLETED_1G
0x13 0x0E STANDARD DTLB_STORE_MISSES.WALK_COMPLETED
0x13 0x10 STANDARD DTLB_STORE_MISSES.WALK_ACTIVE
0x13 0x20 STANDARD DTLB_STORE_MISSES.STLB_HIT
0x20 0x01 AVANZATO OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD
0x20 0x02 AVANZATO OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD
0x20 0x04 AVANZATO OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO
0x20 0x08 AVANZATO OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD
0x20 0x10 AVANZATO OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD
0x21 0x01 AVANZATO OFFCORE_REQUESTS.DEMAND_DATA_RD
0x21 0x02 AVANZATO OFFCORE_REQUESTS.DEMAND_CODE_RD
0x21 0x04 AVANZATO OFFCORE_REQUESTS.DEMAND_RFO
0x21 0x08 AVANZATO OFFCORE_REQUESTS.DATA_RD
0x21 0x10 AVANZATO OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD
0x21 0x80 AVANZATO OFFCORE_REQUESTS.ALL_REQUESTS
0x23 0x40 STANDARD L2_TRANS.L2_WB
0x24 0x21 STANDARD L2_RQSTS.DEMAND_DATA_RD_MISS
0x24 0x22 STANDARD L2_RQSTS.RFO_MISS
0x24 0x24 STANDARD L2_RQSTS.CODE_RD_MISS
0x24 0x27 STANDARD L2_RQSTS.ALL_DEMAND_MISS
0x24 0x28 STANDARD L2_RQSTS.SWPF_MISS
0x24 0x30 STANDARD L2_RQSTS.HWPF_MISS
0x24 0x3F STANDARD L2_RQSTS.MISS
0x24 0xC1 STANDARD L2_RQSTS.DEMAND_DATA_RD_HIT
0x24 0xC2 STANDARD L2_RQSTS.RFO_HIT
0x24 0xC4 STANDARD L2_RQSTS.CODE_RD_HIT
0x24 0xC8 STANDARD L2_RQSTS.SWPF_HIT
0x24 0xDF STANDARD L2_RQSTS.HIT
0x24 0xE1 STANDARD L2_RQSTS.ALL_DEMAND_DATA_RD
0x24 0xE2 STANDARD L2_RQSTS.ALL_RFO
0x24 0xE4 STANDARD L2_RQSTS.ALL_CODE_RD
0x24 0xE7 STANDARD L2_RQSTS.ALL_DEMAND_REFERENCES
0x24 0xF0 STANDARD L2_RQSTS.ALL_HWPF
0x24 0xFF STANDARD L2_RQSTS.REFERENCES
0x25 0x1F STANDARD L2_LINES_IN.ALL
0x26 0x01 STANDARD L2_LINES_OUT.SILENT
0x26 0x02 STANDARD L2_LINES_OUT.NON_SILENT
0x26 0x04 STANDARD L2_LINES_OUT.USELESS_HWPF
0x2D 0x01 AVANZATO XQ.FULL_CYCLES
0x2E 0x41 AVANZATO LONGEST_LAT_CACHE.MISS
0x2E 0x4F AVANZATO LONGEST_LAT_CACHE.REFERENCE
0x3C 0x00 ARCHITETTONICO CPU_CLK_UNHALTED.THREAD_P
0x3C 0x01 ARCHITETTONICO CPU_CLK_UNHALTED.REF_TSC_P
0x40 0x01 STANDARD SW_PREFETCH_ACCESS.NTA
0x40 0x02 STANDARD SW_PREFETCH_ACCESS.T0
0x40 0x04 STANDARD SW_PREFETCH_ACCESS.T1_T2
0x40 0x08 STANDARD SW_PREFETCH_ACCESS.PREFETCHW
0x40 0xF STANDARD SW_PREFETCH_ACCESS.ANY
0x43 0xFD STANDARD MEM_LOAD_COMPLETED.L1_MISS_ANY
0x44 0x01 STANDARD MEM_STORE_RETIRED.L2_HIT
0x47 0x02 STANDARD MEMORY_ACTIVITY.CYCLES_L1D_MISS
0x47 0x03 STANDARD MEMORY_ACTIVITY.STALLS_L1D_MISS
0x47 0x05 STANDARD MEMORY_ACTIVITY.STALLS_L2_MISS
0x47 0x09 AVANZATO MEMORY_ACTIVITY.STALLS_L3_MISS
0x48 0x01 STANDARD L1D_PEND_MISS.PENDING
0x48 0x02 STANDARD L1D_PEND_MISS.FB_FULL
0x48 0x04 STANDARD L1D_PEND_MISS.L2_STALLS
0x4C 0x01 STANDARD LOAD_HIT_PREFETCH.SWPF
0x51 0x01 STANDARD L1D.REPLACEMENT
0x51 0x20 STANDARD L1D.HWPF_MISS
0x54 0x01 AVANZATO TX_MEM.ABORT_CONFLICT
0x54 0x02 AVANZATO TX_MEM.ABORT_CAPACITY_WRITE
0x54 0x80 AVANZATO TX_MEM.ABORT_CAPACITY_READ
0x60 0x01 STANDARD BACLEARS.ANY
0x61 0x02 STANDARD DSB2MITE_SWITCHES.PENALTY_CYCLES
0x75 0x01 STANDARD INST_DECODED.DECODERS
0x76 0x01 STANDARD UOPS_DECODED.DEC0_UOPS
0x79 0x04 STANDARD IDQ.MITE_CYCLES_ANY
0x79 0x08 STANDARD IDQ.DSB_CYCLES_ANY
0x79 0x20 STANDARD IDQ.MS_CYCLES_ANY
0x80 0x04 STANDARD ICACHE_DATA.STALLS
0x83 0x04 STANDARD ICACHE_TAG.STALLS
0x87 0x01 STANDARD DECODE.LCP
0x87 0x02 STANDARD DECODE.MS_BUSY
0x9C 0x01 STANDARD IDQ_UOPS_NOT_DELIVERED.CORE
0xA2 0x02 STANDARD RESOURCE_STALLS.SCOREBOARD
0xA2 0x08 STANDARD RESOURCE_STALLS.SB
0xA3 0x01 STANDARD CYCLE_ACTIVITY.CYCLES_L2_MISS
0xA3 0x02 AVANZATO CYCLE_ACTIVITY.CYCLES_L3_MISS
0xA3 0x04 STANDARD CYCLE_ACTIVITY.STALLS_TOTAL
0xA3 0x05 STANDARD CYCLE_ACTIVITY.STALLS_L2_MISS
0xA3 0x06 AVANZATO CYCLE_ACTIVITY.STALLS_L3_MISS
0xA3 0x08 STANDARD CYCLE_ACTIVITY.CYCLES_L1D_MISS
0xA3 0x0C STANDARD CYCLE_ACTIVITY.STALLS_L1D_MISS
0xA3 0x10 STANDARD CYCLE_ACTIVITY.CYCLES_MEM_ANY
0xA4 0x01 ARCHITETTONICO TOPDOWN.SLOTS_P
0xA4 0x02 STANDARD TOPDOWN.BACKEND_BOUND_SLOTS
0xA4 0x04 STANDARD TOPDOWN.BAD_SPEC_SLOTS
0xA4 0x08 STANDARD TOPDOWN.BR_MISPREDICT_SLOTS
0xA4 0x10 STANDARD TOPDOWN.MEMORY_BOUND_SLOTS
0xA5 0x01 STANDARD RS.EMPTY_RESOURCE
0xA5 0x07 STANDARD RS.EMPTY
0xA6 0x02 STANDARD EXE_ACTIVITY.1_PORTS_UTIL
0xA6 0x04 STANDARD EXE_ACTIVITY.2_PORTS_UTIL
0xA6 0x08 STANDARD EXE_ACTIVITY.3_PORTS_UTIL
0xA6 0x10 STANDARD EXE_ACTIVITY.4_PORTS_UTIL
0xA6 0x21 STANDARD EXE_ACTIVITY.BOUND_ON_LOADS
0xA6 0x40 STANDARD EXE_ACTIVITY.BOUND_ON_STORES
0xA6 0x80 STANDARD EXE_ACTIVITY.EXE_BOUND_0_PORTS
0xA6 0xC STANDARD EXE_ACTIVITY.2_3_PORTS_UTIL
0xA8 0x01 STANDARD LSD.CYCLES_ACTIVE
0xAD 0x01 STANDARD INT_MISC.RECOVERY_CYCLES
0xAD 0x10 STANDARD INT_MISC.UOP_DROPPING
0xAD 0x20 STANDARD INT_MISC.MBA_STALLS
0xAD 0x80 STANDARD INT_MISC.CLEAR_RESTEER_CYCLES
0xAE 0x01 STANDARD UOPS_ISSUED.ANY
0xB0 0x01 STANDARD ARITH.FPDIV_ACTIVE
0xB0 0x08 STANDARD ARITH.IDIV_ACTIVE
0xB0 0x09 STANDARD ARITH.DIV_ACTIVE
0xB1 0x01 STANDARD UOPS_EXECUTED.CYCLES_GE_1
0xB1 0x02 STANDARD UOPS_EXECUTED.CORE
0xB1 0x10 STANDARD UOPS_EXECUTED.X87
0xB2 0x01 STANDARD UOPS_DISPATCHED.PORT_0
0xB2 0x02 STANDARD UOPS_DISPATCHED.PORT_1
0xB2 0x04 STANDARD UOPS_DISPATCHED.PORT_2_3_10
0xB2 0x10 STANDARD UOPS_DISPATCHED.PORT_4_9
0xB2 0x20 STANDARD UOPS_DISPATCHED.PORT_5_11
0xB2 0x40 STANDARD UOPS_DISPATCHED.PORT_6
0xB2 0x80 STANDARD UOPS_DISPATCHED.PORT_7_8
0xB3 0x01 STANDARD FP_ARITH_DISPATCHED.PORT_0
0xB3 0x02 STANDARD FP_ARITH_DISPATCHED.PORT_1
0xB3 0x04 STANDARD FP_ARITH_DISPATCHED.PORT_5
0xB7 0x02 STANDARD EXE.AMX_BUSY
0xC0 0x00 ARCHITETTONICO INST_RETIRED.ANY_P
0xC0 0x02 STANDARD INST_RETIRED.NOP
0xC0 0x08 STANDARD INST_RETIRED.REP_ITERATION
0xC0 0x10 STANDARD INST_RETIRED.MACRO_FUSED
0xC1 0x02 STANDARD ASSISTS.FP
0xC1 0x04 STANDARD ASSISTS.HARDWARE
0xC1 0x08 STANDARD ASSISTS.PAGE_FAULT
0xC1 0x10 STANDARD ASSISTS.SSE_AVX_MIX
0xC1 0x1B STANDARD ASSISTS.ANY
0xC2 0x01 STANDARD UOPS_RETIRED.HEAVY
0xC2 0x02 STANDARD UOPS_RETIRED.SLOTS
0xC3 0x01 STANDARD MACHINE_CLEARS.COUNT
0xC3 0x02 STANDARD MACHINE_CLEARS.MEMORY_ORDERING
0xC3 0x04 STANDARD MACHINE_CLEARS.SMC
0xC4 0x00 ARCHITETTONICO BR_INST_RETIRED.ALL_BRANCHES
0xC4 0x01 STANDARD BR_INST_RETIRED.COND_TAKEN
0xC4 0x02 STANDARD BR_INST_RETIRED.NEAR_CALL
0xC4 0x08 STANDARD BR_INST_RETIRED.NEAR_RETURN
0xC4 0x10 STANDARD BR_INST_RETIRED.COND_NTAKEN
0xC4 0x11 STANDARD BR_INST_RETIRED.COND
0xC4 0x20 STANDARD BR_INST_RETIRED.NEAR_TAKEN
0xC4 0x40 STANDARD BR_INST_RETIRED.FAR_BRANCH
0xC4 0x80 STANDARD BR_INST_RETIRED.INDIRECT
0xC5 0x00 ARCHITETTONICO BR_MISP_RETIRED.ALL_BRANCHES
0xC5 0x01 STANDARD BR_MISP_RETIRED.COND_TAKEN
0xC5 0x02 STANDARD BR_MISP_RETIRED.INDIRECT_CALL
0xC5 0x08 STANDARD BR_MISP_RETIRED.RET
0xC5 0x10 STANDARD BR_MISP_RETIRED.COND_NTAKEN
0xC5 0x11 STANDARD BR_MISP_RETIRED.COND
0xC5 0x20 STANDARD BR_MISP_RETIRED.NEAR_TAKEN
0xC5 0x41 STANDARD BR_MISP_RETIRED.COND_TAKEN_COST
0xC5 0x42 STANDARD BR_MISP_RETIRED.INDIRECT_CALL_COST
0xC5 0x44 STANDARD BR_MISP_RETIRED.ALL_BRANCHES_COST
0xC5 0x48 STANDARD BR_MISP_RETIRED.RET_COST
0xC5 0x50 STANDARD BR_MISP_RETIRED.COND_NTAKEN_COST
0xC5 0x51 STANDARD BR_MISP_RETIRED.COND_COST
0xC5 0x60 STANDARD BR_MISP_RETIRED.NEAR_TAKEN_COST
0xC5 0x80 STANDARD BR_MISP_RETIRED.INDIRECT
0xC5 0xC0 STANDARD BR_MISP_RETIRED.INDIRECT_COST
0xC7 0x01 STANDARD FP_ARITH_INST_RETIRED.SCALAR_DOUBLE
0xC7 0x02 STANDARD FP_ARITH_INST_RETIRED.SCALAR_SINGLE
0xC7 0x03 STANDARD FP_ARITH_INST_RETIRED.SCALAR
0xC7 0x04 STANDARD FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE
0xC7 0x08 STANDARD FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE
0xC7 0x10 STANDARD FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE
0xC7 0x18 STANDARD FP_ARITH_INST_RETIRED.4_FLOPS
0xC7 0x20 STANDARD FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE
0xC7 0x40 STANDARD FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE
0xC7 0x60 STANDARD FP_ARITH_INST_RETIRED.8_FLOPS
0xC7 0x80 STANDARD FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE
0xC7 0xFC STANDARD FP_ARITH_INST_RETIRED.VECTOR
0xC9 0x01 AVANZATO RTM_RETIRED.START
0xC9 0x02 AVANZATO RTM_RETIRED.COMMIT
0xC9 0x04 AVANZATO RTM_RETIRED.ABORTED
0xC9 0x08 AVANZATO RTM_RETIRED.ABORTED_MEM
0xC9 0x20 AVANZATO RTM_RETIRED.ABORTED_UNFRIENDLY
0xC9 0x40 AVANZATO RTM_RETIRED.ABORTED_MEMTYPE
0xC9 0x80 AVANZATO RTM_RETIRED.ABORTED_EVENTS
0xCF 0x01 STANDARD FP_ARITH_INST_RETIRED2.SCALAR_HALF
0xCF 0x02 STANDARD FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF
0xCF 0x03 STANDARD FP_ARITH_INST_RETIRED2.SCALAR
0xCF 0x04 STANDARD FP_ARITH_INST_RETIRED2.128B_PACKED_HALF
0xCF 0x08 STANDARD FP_ARITH_INST_RETIRED2.256B_PACKED_HALF
0xCF 0x10 STANDARD FP_ARITH_INST_RETIRED2.512B_PACKED_HALF
0xCF 0x1C STANDARD FP_ARITH_INST_RETIRED2.VECTOR
0xD0 0x09 STANDARD MEM_INST_RETIRED.STLB_HIT_LOADS
0xD0 0x0A STANDARD MEM_INST_RETIRED.STLB_HIT_STORES
0xD0 0x11 STANDARD MEM_INST_RETIRED.STLB_MISS_LOADS
0xD0 0x12 STANDARD MEM_INST_RETIRED.STLB_MISS_STORES
0xD0 0x21 STANDARD MEM_INST_RETIRED.LOCK_LOADS
0xD0 0x41 STANDARD MEM_INST_RETIRED.SPLIT_LOADS
0xD0 0x42 STANDARD MEM_INST_RETIRED.SPLIT_STORES
0xD0 0x81 STANDARD MEM_INST_RETIRED.ALL_LOADS
0xD0 0x82 STANDARD MEM_INST_RETIRED.ALL_STORES
0xD0 0x83 STANDARD MEM_INST_RETIRED.ANY
0xD1 0x01 STANDARD MEM_LOAD_RETIRED.L1_HIT
0xD1 0x02 STANDARD MEM_LOAD_RETIRED.L2_HIT
0xD1 0x04 AVANZATO MEM_LOAD_RETIRED.L3_HIT
0xD1 0x08 STANDARD MEM_LOAD_RETIRED.L1_MISS
0xD1 0x10 STANDARD MEM_LOAD_RETIRED.L2_MISS
0xD1 0x20 AVANZATO MEM_LOAD_RETIRED.L3_MISS
0xD1 0x40 STANDARD MEM_LOAD_RETIRED.FB_HIT
0xD2 0x01 AVANZATO MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS
0xD2 0x02 AVANZATO MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD
0xD2 0x04 AVANZATO MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD
0xD2 0x08 AVANZATO MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE
0xD3 0x01 AVANZATO MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM
0xD3 0x02 AVANZATO MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM
0xD3 0x04 AVANZATO MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM
0xD3 0x08 AVANZATO MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD
0xD4 0x04 STANDARD MEM_LOAD_MISC_RETIRED.UC
0xE0 0x20 STANDARD MISC2_RETIRED.LFENCE
0xE5 0x03 STANDARD MEM_UOP_RETIRED.ANY
0xE7 0x03 STANDARD INT_VEC_RETIRED.ADD_128
0xE7 0x0C STANDARD INT_VEC_RETIRED.ADD_256
0xE7 0x10 STANDARD INT_VEC_RETIRED.VNNI_128
0xE7 0x13 STANDARD INT_VEC_RETIRED.128BIT
0xE7 0x20 STANDARD INT_VEC_RETIRED.VNNI_256
0xE7 0x40 STANDARD INT_VEC_RETIRED.SHUFFLES
0xE7 0x80 STANDARD INT_VEC_RETIRED.MUL_256
0xE7 0xAC STANDARD INT_VEC_RETIRED.256BIT
0xEC 0x10 STANDARD CPU_CLK_UNHALTED.C01
0xEC 0x20 STANDARD CPU_CLK_UNHALTED.C02
0xEC 0x40 STANDARD CPU_CLK_UNHALTED.PAUSE
0xEC 0x70 STANDARD CPU_CLK_UNHALTED.C0_WAIT

NVIDIA Grace

La tabella seguente elenca gli eventi PMU supportati per i processori NVIDIA Grace con core Arm Neoverse V2.

Codice evento Tipo di monitoraggio PMU Nome evento
0x0 ARCHITETTONICO SW_INCR
0x3 ARCHITETTONICO L1D_CACHE_REFILL
0x4 ARCHITETTONICO L1D_CACHE
0x8 ARCHITETTONICO INST_RETIRED
0x10 ARCHITETTONICO BR_MIS_PRED
0x11 ARCHITETTONICO CPU_CYCLES
0x12 ARCHITETTONICO BR_PRED
0x1b ARCHITETTONICO INST_SPEC
0x1e ARCHITETTONICO CHAIN
0x23 ARCHITETTONICO STALL_FRONTEND
0x24 ARCHITETTONICO STALL_BACKEND
0x39 ARCHITETTONICO L1D_CACHE_LMISS_RD
0x3c ARCHITETTONICO STALL
0x40 ARCHITETTONICO L1D_CACHE_RD
0x4006 ARCHITETTONICO L1I_CACHE_LMISS
0x8006 ARCHITETTONICO SVE_INST_SPEC
0x0 STANDARD SW_INCR
0x1 STANDARD L1I_CACHE_REFILL
0x2 STANDARD L1I_TLB_REFILL
0x3 STANDARD L1D_CACHE_REFILL
0x4 STANDARD L1D_CACHE
0x5 STANDARD L1D_TLB_REFILL
0x8 STANDARD INST_RETIRED
0x9 STANDARD EXC_TAKEN
0xa STANDARD EXC_RETURN
0xb STANDARD CID_WRITE_RETIRED
0x10 STANDARD BR_MIS_PRED
0x11 STANDARD CPU_CYCLES
0x12 STANDARD BR_PRED
0x13 STANDARD MEM_ACCESS
0x14 STANDARD L1I_CACHE
0x15 STANDARD L1D_CACHE_WB
0x16 STANDARD L2D_CACHE
0x17 STANDARD L2D_CACHE_REFILL
0x18 STANDARD L2D_CACHE_WB
0x19 STANDARD BUS_ACCESS
0x1b STANDARD INST_SPEC
0x1c STANDARD TTBR_WRITE_RETIRED
0x1d STANDARD BUS_CYCLES
0x1e STANDARD CHAIN
0x20 STANDARD L2D_CACHE_ALLOCATE
0x21 STANDARD BR_RETIRED
0x22 STANDARD BR_MIS_PRED_RETIRED
0x23 STANDARD STALL_FRONTEND
0x24 STANDARD STALL_BACKEND
0x25 STANDARD L1D_TLB
0x26 STANDARD L1I_TLB
0x2d STANDARD L2D_TLB_REFILL
0x2f STANDARD L2D_TLB
0x31 STANDARD REMOTE_ACCESS
0x34 STANDARD DTLB_WALK
0x35 STANDARD ITLB_WALK
0x39 STANDARD L1D_CACHE_LMISS_RD
0x3a STANDARD OP_RETIRED
0x3b STANDARD OP_SPEC
0x3c STANDARD STALL
0x3d STANDARD STALL_SLOT_BACKEND
0x3e STANDARD STALL_SLOT_FRONTEND
0x3f STANDARD STALL_SLOT
0x40 STANDARD L1D_CACHE_RD
0x41 STANDARD L1D_CACHE_WR
0x42 STANDARD L1D_CACHE_REFILL_RD
0x43 STANDARD L1D_CACHE_REFILL_WR
0x44 STANDARD L1D_CACHE_REFILL_INNER
0x45 STANDARD L1D_CACHE_REFILL_OUTER
0x46 STANDARD L1D_CACHE_WB_VICTIM
0x47 STANDARD L1D_CACHE_WB_CLEAN
0x48 STANDARD L1D_CACHE_INVAL
0x4c STANDARD L1D_TLB_REFILL_RD
0x4d STANDARD L1D_TLB_REFILL_WR
0x4e STANDARD L1D_TLB_RD
0x4f STANDARD L1D_TLB_WR
0x50 STANDARD L2D_CACHE_RD
0x51 STANDARD L2D_CACHE_WR
0x52 STANDARD L2D_CACHE_REFILL_RD
0x53 STANDARD L2D_CACHE_REFILL_WR
0x56 STANDARD L2D_CACHE_WB_VICTIM
0x57 STANDARD L2D_CACHE_WB_CLEAN
0x58 STANDARD L2D_CACHE_INVAL
0x5c STANDARD L2D_TLB_REFILL_RD
0x5d STANDARD L2D_TLB_REFILL_WR
0x5e STANDARD L2D_TLB_RD
0x5f STANDARD L2D_TLB_WR
0x60 STANDARD BUS_ACCESS_RD
0x61 STANDARD BUS_ACCESS_WR
0x66 STANDARD MEM_ACCESS_RD
0x67 STANDARD MEM_ACCESS_WR
0x68 STANDARD UNALIGNED_LD_SPEC
0x69 STANDARD UNALIGNED_ST_SPEC
0x6a STANDARD UNALIGNED_LDST_SPEC
0x6c STANDARD LDREX_SPEC
0x6d STANDARD STREX_PASS_SPEC
0x6e STANDARD STREX_FAIL_SPEC
0x6f STANDARD STREX_SPEC
0x70 STANDARD LD_SPEC
0x71 STANDARD ST_SPEC
0x73 STANDARD DP_SPEC
0x74 STANDARD ASE_SPEC
0x75 STANDARD VFP_SPEC
0x76 STANDARD PC_WRITE_SPEC
0x77 STANDARD CRYPTO_SPEC
0x78 STANDARD BR_IMMED_SPEC
0x79 STANDARD BR_RETURN_SPEC
0x7a STANDARD BR_INDIRECT_SPEC
0x7c STANDARD ISB_SPEC
0x7d STANDARD DSB_SPEC
0x7e STANDARD DMB_SPEC
0x81 STANDARD EXC_UNDEF
0x82 STANDARD EXC_SVC
0x83 STANDARD EXC_PABORT
0x84 STANDARD EXC_DABORT
0x86 STANDARD EXC_IRQ
0x87 STANDARD EXC_FIQ
0x88 STANDARD EXC_SMC
0x8a STANDARD EXC_HVC
0x8b STANDARD EXC_TRAP_PABORT
0x8c STANDARD EXC_TRAP_DABORT
0x8d STANDARD EXC_TRAP_OTHER
0x8e STANDARD EXC_TRAP_IRQ
0x8f STANDARD EXC_TRAP_FIQ
0x90 STANDARD RC_LD_SPEC
0x91 STANDARD RC_ST_SPEC
0x4004 STANDARD CNT_CYCLES
0x4005 STANDARD STALL_BACKEND_MEM
0x4006 STANDARD L1I_CACHE_LMISS
0x4009 STANDARD L2D_CACHE_LMISS_RD
0x4020 STANDARD LDST_ALIGN_LAT
0x4021 STANDARD LD_ALIGN_LAT
0x4022 STANDARD ST_ALIGN_LAT
0x8005 STANDARD ASE_INST_SPEC
0x8006 STANDARD SVE_INST_SPEC
0x8014 STANDARD FP_HP_SPEC
0x8018 STANDARD FP_SP_SPEC
0x801c STANDARD FP_DP_SPEC
0x8074 STANDARD SVE_PRED_SPEC
0x8075 STANDARD SVE_PRED_EMPTY_SPEC
0x8076 STANDARD SVE_PRED_FULL_SPEC
0x8077 STANDARD SVE_PRED_PARTIAL_SPEC
0x8079 STANDARD SVE_PRED_NOT_FULL_SPEC
0x80bc STANDARD SVE_LDFF_SPEC
0x80bd STANDARD SVE_LDFF_FAULT_SPEC
0x80c0 STANDARD FP_SCALE_OPS_SPEC
0x80c1 STANDARD FP_FIXED_OPS_SPEC
0x80e3 STANDARD ASE_SVE_INT8_SPEC
0x80e7 STANDARD ASE_SVE_INT16_SPEC
0x80eb STANDARD ASE_SVE_INT32_SPEC
0x80ef STANDARD ASE_SVE_INT64_SPEC

Prezzi

Non sono previsti costi per l'utilizzo dell'unità di monitoraggio delle prestazioni in un'istanza di Compute.

Limitazioni

Puoi attivare il tipo di PMU avanzata solo nelle istanze C4 o M4 che utilizzano uno dei seguenti tipi di macchine:

  • Qualsiasi tipo di macchina C4 con 144 o 288 vCPU

  • Uno dei seguenti tipi di macchine M4:

    • m4-megamem-112

    • m4-megamem-224

    • m4-ultramem-56

    • m4-ultramem-112

    • m4-ultramem-224

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